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INTEGRATED CIRCUITS
74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State)
Product specification IC24 Data Handbook 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
FEATURES
* Wide supply voltage range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A. * CMOS low power consumption * Direct interface with TTL levels * Current drive 24 mA at 3.0 V * MultibyteTMflow-through standard pin-out architecture * Low inductance multiple VCC and GND pins to minimize noise and
ground bounce
DESCRIPTION
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (CP) input, an output-enable (OE) input, a Master reset (MR) input and a clock-enable( CE) input are provided for each total 9-bit section. With the clock-enable (CE) input LOW, the D-type flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. Taking CE HIGH disables the clock buffer, thus latching the outputs. Taking the Master reset (MR) input LOW causes all the Q outputs to go LOW independently of the clock. When OE is LOW, the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
* All data inputs have bus hold * Output drive capability 50 transmission lines @ 85C
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf 2.5ns SYMBOL tPHL/tPLH Fmax CI CPD PARAMETER Propagation delay CP to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF TYPICAL 2.1 2.1 300 350 5.0 16 10 UNIT ns MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type II 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ALVCH16823 DL 74ALVCH16823 DGG NORTH AMERICA ACH16823 DL ACH16823 DGG DWG NUMBER SOT371-1 SOT364-1
1998 Jul 29
2
853-2100 19800
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
PIN DESCRIPTION
PIN NUMBER 2, 27 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26 56, 29 55, 30 1, 28 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1OE, 2OE 1D0-1D8 2D0-2D8 1Q0-1Q8 2Q0-2Q8 1CP, 2CP 1CE, 2CE 1MR, 2MR GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Clock pulse input (active rising edge) Clock enable input (active-Low) Master reset input (active-Low) Ground (0V) Positive supply voltage
PIN CONFIGURATION
1MR 1OE 1Q0 GND 1Q1 1Q2 VCC 1Q3 1Q4 1Q5 GND 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2OE 2MR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1CP 1CE 1D0 GND 1D1 1D2 VCC 1D3 1D4 1D5 GND 1D6 1D7 1D8 2D0 2D1 2D2 GND 2D3
LOGIC SYMBOL
1 28 2 27
1MR 2MR 1OE 2OE 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
1CP 2CP 1CE 2CE 48 29 55 30
SW00341
2D4 2D5 VCC 2D6 2D7 GND 2D8 2CE 2CP
SH00014
1998 Jul 29
3
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
LOGIC SYMBOL (IEEE/IEC)
1OE 1MR 1CE 1CP 2OE 2MR 2CE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2 1 55 56 27 28 30 29 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 8D 5, 6 EN1 R2 G3 3C4 EN5 R6 G7 7C8 4D 1, 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 25 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
BUS HOLD CIRCUIT
VCC
Data Input
To internal circuit
SW00044
SH00015
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP CP CP CP CP nD CP CP CP CP CP
nD
nD
nD
nD
nD
nD
nD
nD
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
nMR
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8
n = 1 or 2
SH00016
1998 Jul 29
4
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
FUNCTION TABLE
INPUTS nOE L L L L L H h L l X Z = = = = = = = nMR L H H H H nCE X L L L H nCP X L X nDx X h l X X OUTPUT nQx L H L Q0 Q0 Disable outputs Hold Clear Load and read data OPERATING MODES
H X X X X Z HIGH voltage level HIGH voltage level one set-up time prior to the Low-to-High clock transition LOW voltage level LOW voltage level one set-up time prior to the Low-to-High clock transition Don't care HIGH impedance "off" state LOW to High clock transition
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) DC supply voltage (for low-voltage applications) for data input pins VI VO Tamb tr, tf DC Input voltage range for control pins DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V 0 0 -40 0 0 CONDITIONS MIN 2.3 3.0 1.2 0 MAX 2.7 V 3.6 3.6 VCC 5.5 VCC +85 20 10 V V V V C ns/V UNIT
VCC
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC in ut voltage input DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic medium-shrink (SSOP) -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 11.3 mW/K above +55C derate linearly with 8 mW/K VI t0 For control pins1 For data inputs1 CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +5.5 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 850 600 V mA V mA mA C mW UNIT V mA
VO uVCC or VO t 0 Note 1 VO = 0 to VCC
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VCC = 1.2V VIH HIGH level Input voltage In ut VCC = 1.8V VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 1.2V VIL LOW level In ut voltage Input VCC = 1.8V VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 1 8 to 3 6V; VI = VIH or VIL; IO = -100A 1.8 3.6V; VCC = 1.8V; VI = VIH or VIL; IO = -6mA VCC = 2.3V; VI = VIH or VIL; IO = -6mA VOH HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = -12mA VCC = 2.3V; VI = VIH or VIL; IO = -18mA VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 1 8 to 3 6V; VI = VIH or VIL; IO = 100A 1.8 3.6V; VCC = 1.8V; VI = VIH or VIL; IO = 6mA VCC = 2.3V; VI = VIH or VIL; IO = 6mA VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.3V; VI = VIH or VIL; IO = 18mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II Input leakage current per control pin Input leakage current per data pin Input current for common I/O pins VCC = 1.8 to 3.6V; VI = 5.5V or GND VCC = 1.8 to 3.6V; VI = VCC or GND VCC = 1.8 to 2.7V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND VCC = 1.8 to 2.7V; VI = VIH or VIL; VO = VCC or GND VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 2.7V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.3V; VI = 0.7V2 45 75 -45 -75 300 450 -300 -450 -175 VCC = 3.0V; VI = 0.8V2 VCC = 2.3V; VI = 1.7V2 VCC = 3.0V; VI = 2.0V2 VCC = 2.7V2 VCC = 3.6V2 VCC = 2.7V2 VCC = 3.6V2 VCC*0 2 *0.2 VCC*0.4 VCC*0.3 VCC*0.5 VCC*0.6 VCC*0.5 VCC*1.0 TEST CONDITIONS Temp = -40C to +85C MIN VCC 0.7*VCC 1.7 2.0 0.9 1.2 1.5 - 0.9 1.2 1.5 VCC VCC*0.10 VCC*0.08 VCC*0.17 VCC*0.26 VCC*0.14 VCC*0.28 GND 0.09 0.07 0.15 0.23 0.14 0.27 0.1 0.1 0.1 0.1 0.1 0.1 150 - 150 GND 0.2*VCC 0.7 0.8 - - - - - - - 0 20 0.20 0.30 0.20 0.40 0.60 0.40 0.55 5 A 5 10 A 15 5 A 10 750 A A A A A V V V V TYP1 MAX UNIT
IIHZ/IILZ
IOZ
3-State output OFF-state current Additional quiescent supply current given per data I/O pin Bus hold LOW sustaining g current Bus hold HIGH sustaining g current Bus hold LOW overdrive current Bus hold HIGH overdrive current
ICC IBHL IBHH IBHLO IBHHO
NOTES: 1. All typical values are at Tamb = 25C. 2. Valid for data inputs of bus hold parts.
1998 Jul 29
6
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE AND VCC < 2.3V
GND = 0V; tr = tf 2.0ns; CL = 30pF SYMBOL LIMITS PARAMETER Propagation delay nCP to nQn Propagation delay nMR to nQn 3-State output enable time nOEn to nQn 3-State output disable time nOEn to nQn nCP pulse width nMR pulse width, LOW Set up time nDn to nCP Set up time nCE to nCP Hold time nDn to nCP Hold time nCE to nCP Recovery time nMR to nCP WAVEFORM VCC = 2.3 to 2.7V MIN tPLH/tPHL tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tW tSU th trec 1, 5 2, 5 4, 5 4, 5 1, 5 3, 5 35 3, 3, 35 2, 5 1, 5 1.0 1.0 1.0 1.0 3.0 3.0 1.2 1.8 0.8 0.3 1.0 150 TYP1, 2 2.8 2.9 2.8 2.2 1.6 0.4 0.2 -0.2 -0.1 0.2 0.3 300 MAX 4.9 5.0 5.3 4.1 MIN 1.5 1.5 1.5 1.5 4.0 4.0 1.5 2.0 0.6 0.3 0.8 125 VCC = 1.8V TYP1 4.5 4.6 4.4 3.3 2.0 0.8 0.2 -0.2 -0.2 0.2 0.2 250 MAX 7.5 7.4 7.7 5.5 VCC = 1.2V TYP1 10.6 9.9 10.4 6.7 ns ns ns ns ns ns ns ns MHz UNIT
Fmax Maximum clock pulse frequency NOTE: 1. All typical values are measured at Tamb = 25C. 2. Typical value is measured at VCC = 2.5V.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf 2.5ns; CL = 50pF SYMBOL LIMITS PARAMETER Propagation delay nCP to nQn Propagation delay nMR to nQn 3-State output enable time nOEn to nQn 3-State output disable time nOEn to nQn nCP pulse width HIGH or LOW nMR pulse width HIGH or LOW Set up time nDn to nCP Set up time nCE to nCP Hold time nDn to nCP Hold time nCE to nCP Recovery time nMR to nCP WAVEFORM VCC = 3.0 0.3V MIN tPLH/tPHL tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tW tSU th trec 1, 5 2, 5 4, 5 4, 5 1, 5 3, 5 3, 35 3, 35 2, 5 1, 5 1.0 1.0 1.0 1.0 2.5 2.5 1.2 1.5 0.8 0.5 1.0 200 TYP1, 2 2.5 2.6 2.5 2.8 1.4 0.3 0.2 -0.1 0.0 0.1 0.2 350 MAX 3.7 4.0 4.3 3.9 MIN 1.0 1.0 1.0 1.0 3.0 3.0 1.5 1.9 0.6 0.4 0.8 150 VCC = 2.7V TYP1 2.7 3.1 3.1 3.1 1.6 0.6 0.4 -0.1 -0.2 0.1 0.1 300 MAX 4.3 4.6 5.2 4.3 ns ns ns ns ns ns ns ns MHz UNIT
Fmax Maximum clock pulse frequency NOTES: 1. All typical values are measured at Tamb = 25C. 2. Typical value is measured at VCC = 3.3V.
1998 Jul 29
7
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE
VM = 0.5 VCC VX = VOL + 0.15V VY = VOH -0.15V VOL and VOH are the typical output voltage drop that occur with the output load. V =V CC I
VI nOE INPUT GND VM
AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE
VM = 1.5 V VX = VOL + 0.3V VY = VOH -0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I
1/fMAX
tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VX VOL tPHZ VOH
tPZL
VM
tPZH
nCP
VM tw tPHL
VM tPLH
3.0V or VCC whichever is less 0V
OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled
VY VM
outputs disabled
outputs enabled
VOH nQn VM VM 0V
SW00308
Waveform 4. 3-State Enable and Disable Times
SH00017
TEST CIRCUIT
VCC S1 2Waveform 1. Clock (nCP) to Output (nQn) Propagation Delays, Clock Pulse Width, and Maximum Clock Pulse Frequency
nMR
VM tw
VM tREC VM tPHL
3.0V or VCC whichever is less 0V 3.0V or VCC whichever is less 0V VOH
VIN PULSE GENERATOR
nCP
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH SWITCH Open 2nQn
VM 0V SH00018
Waveform 2. Master Reset (MR) Pulse WIdth, MR to Output propagation Delay and MR to Clock Recovery Time
VI nCP INPUT GND VI nCE, nDn INPUT GND VOH nQn OUTPUT VOL VM VM VM tsu th tsu th
DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SW00047
Waveform 5. Load circuitry for switching times
NOTE: The data set-up and hold times for Dn or CE input to the CP input SH00155
Waveform 3. Data Setup and Hold Times for the Dn or CE input to the CP input
1998 Jul 29
8
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ALVCH16823
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 Jul 29
9
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ALVCH16823
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Jul 29
10
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ALVCH16823
NOTES
1998 Jul 29
11
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ALVCH16823
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04554
Philips Semiconductors
1998 Jul 29 12

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